The present invention pertains to forming design features such as trenches and vias in a semiconductor substrate and, more particularly, pertains to a methodology for varying the depth of the design features by the selective placement of vias and by varying ashing conditions and the organic planarizing layer.
Semiconductor devices include trenches and vias for forming and connecting various semiconductor devices. These trenches and vias should have a depth that matches the design requirements for the semiconductors being manufactured. Additionally, the trenches and vias may have different depths from device to device which makes manufacturing of these devices costly and time consuming.